FIGS. 1A˜1D schematically illustrate the structure and the equivalent circuit of a conventional erasable programmable non-volatile memory. The conventional erasable programmable non-volatile memory is disclosed in U.S. Pat. No. 8,941,167. FIG. 1A is a schematic top view of a conventional erasable programmable non-volatile memory. FIG. 1B is a schematic cross-sectional view illustrating the conventional erasable programmable non-volatile memory of FIG. 1A and taken along a first direction (a1-a2). FIG. 1C is a schematic cross-sectional view illustrating the erasable programmable non-volatile memory of FIG. 1A and taken along a second direction (b1-b2). FIG. 1D is a schematic equivalent circuit diagram of the conventional erasable programmable non-volatile memory.
As shown in FIGS. 1A and 1B, the erasable programmable non-volatile memory comprises two serially-connected p-type transistors. These two p-type transistors are constructed in an n-well region (NW). Three p-type doped regions 31, 32 and 33 are formed in the n-well region (NW). In addition, two polysilicon gates 34 and 36 are spanned over the areas between the three p-type doped regions 31, 32 and 33.
The first p-type transistor is used as a select transistor, and the polysilicon gate 34 (also referred as a select gate) of the first p-type transistor is connected to a select gate voltage VSG. The p-type doped region 31 is connected to a source line voltage VSL. The p-type doped region 32 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor. The second p-type transistor is a floating gate transistor. The polysilicon gate 36 (also referred as a floating gate) is disposed over the second p-type transistor. The p-type doped region 33 is connected to a bit line voltage VBL. Moreover, the n-well region (NW) is connected to an n-well voltage VNW.
As shown in FIGS. 1A and 10, the erasable programmable non-volatile memory further comprises an n-type transistor. The n-type transistor is composed of the floating gate 36 and an erase gate region 35. The n-type transistor is constructed in a p-well region (PW). An n-type doped region 38 is formed in the p-well region (PW). That is, the erase gate region 35 contains the p-well region (PW) and the n-type doped region 38.
As shown in FIG. 1A, the floating gate 36 is extended externally and located near the erase gate region 35. Consequently, the floating gate 36 is also the gate terminal of the n-type transistor. Moreover, the n-type doped region 38 may be considered as a combination of an n-type doped source region and an n-type doped drain region. The n-type doped region 38 is connected to an erase line voltage VEL. In addition, the p-well region (PW) is connected to a p-well voltage VPW. As shown in FIG. 1C, the erase gate region 35 and the n-well region (NW) are isolated from each other by a shallow trench isolation (STI) structure 39.
The operating principles of the conventional erasable programmable non-volatile memory will be described as follows.
During a program cycle, proper voltages are provided to the corresponding terminals. In a case that the electrons (e.g. hot carriers) are transmitted through a channel region corresponding to the floating gate transistor, the hot carriers are injected into the floating gate 36 and are stored in the floating gate 36. Consequently, the program action is completed.
During an erase cycle, proper voltages are provided to the corresponding terminals. The electrons stored in the floating gate are removed from the floating gate 36 and discharged out of the nonvolatile memory through the n-type doped region 38. Consequently, after the erased state, no electrons are stored in the floating gate 36.
In a read cycle, proper voltages are provided to the corresponding terminals. Depending on whether the electrons are stored in the floating gate 36, different magnitudes of the read current IR are acquired. That is, in the read state, the storage state of the nonvolatile memory may be realized according to the read current IR.
As mentioned above, the conventional erasable programmable non-volatile memory has a twin-well structure, thus the overall size of the conventional erasable programmable non-volatile memory is large. During the program cycle, the electrons (e.g hot carriers) are injected into the floating gate 36 and stored into the floating gate 36 according to a channel hot electron injection (CHE) effect.